1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a field effect type transistor.
2. Description of the Related Art
Miniaturization of a semiconductor integrated circuit that incorporates field effect type transistors (FETs) has been accompanied by a need to miniaturize such FETS. However, such miniaturization brings about a reduction in a driving force, i.e., drain current, which in turn leads to a reduction in operation speed of a semiconductor device. Thus, there is an urgent need to achieve miniaturization while maintaining driving force.
As means for increasing the driving force of the transistor, there are available methods of achieving low resistance by metal-saliciding a source/drain section, using an extremely shallow and high-concentration diffusion layer, and the like. These methods are designed to improve performance when a planar (two-dimensional) device structure is maintained.
Additionally, there has been invented a method of increasing a driving force by employing a three-dimensional structure of a channel region such as a fin-type FET to increase a physical channel width. In the case of the fin-type FET, however, a fin width must be reduced to improve cut-off characteristics of the transistor, and accordingly the fin width must be smaller than a minimum design rule size. Thus, an additional process having high technical hurdles is necessary for manufacturing.
Jpn. Pat. Appln. KOKAI Publication No. 2002-118255 shows an example of a three-dimensional structure of a channel region. For example, in a paragraph (0110) of this Patent Application Document, a MOS-type transistor is described with reference to FIGS. 16A to 16C of this prior art document. That is, it is described that fences 13 are arranged in parallel on a substrate, a contact with a source/drain region 17 is made common, and a gate electrode 16 is also made common, thereby achieving a large channel width of the three dimensional structure.
Further, U.S. Pat. No. 6,853,031 B2 describes a structure of a trapezoid-triple-gate FET including a plurality of trapezoid pillars juxtaposed on a semiconductor substrate. Each trapezoid pillar has a source, a channel region and a drain so as to increase a channel width for increasing the channel conductance.
However, there is a demand for a field effect type transistor (FET) which can obtain a driving force much larger than that of the MOS-type transistor described in the prior art, or achieve miniaturization. Further, there is a demand for a field effect transistor having an improved cut-off characteristic.